Field
The present invention relates to integrated circuits and, more specifically, to integrated circuits having programmable non-volatile memory cells.
Description of Related Art
This section introduces aspects that may help facilitate a better understanding of aspects of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
A one-time-programmable (OTP) non-volatile memory cell is a set of integrated circuitry that can be programmed one time to have a permanent binary value. In one type of OTP cell, the “unprogrammed” cell has a default, low-current state when the OTP cell is read, which, depending on the logic applied, can be interpreted as corresponding to either a binary value of 0 or a binary value of 1, while the “programmed” cell has a permanent, high-current state when the OTP cell is read, which would be interpreted as corresponding to the other binary value. OTP cells have many different applications, including use in non-volatile configuration memory (NVCM).
FIG. 1 is a schematic circuit diagram of a (2×2) array 100 of four conventional n-type OTP cells 110, where each OTP cell 110 comprises an n-type access (transistor) device 112 and an n-type anti-fuse (transistor) device 114. As indicated in FIG. 1, the (2×2) array 100 is part of a larger array (not shown), where the four OTP cells 110 are located in the mth and (m+1)th columns and the nth and (n+1)th rows of that larger array.
As shown in FIG. 1, for each OTP cell 110, the gate (G) of the access device 112 is connected to a corresponding read word line WR, the gate of the anti-fuse device 114 is connected to a corresponding programming word line WP, the source (S) of the access device 112 is connected to a corresponding bit line BL, the drain (D) of the access device 112 is connected to the source of the anti-fuse device 114, and the drain of the anti-fuse device 114 is floating (i.e., not connected to any driven voltage node). In terms of the disclosure, the term “voltage level” as being applied to a particular line, such as a write line, includes floating that line, as well as actively applying a voltage of some polarity (see e.g., FIG. 7) Each OTP cell 110 is accessed via the corresponding read and programming word lines WR and WP, and the program state of each OTP cell 110 is determined by sensing the current in the corresponding bit line BL using sense circuitry (not shown) connected to the bit line. One or more OTP cells 110 in array 100 can be programmed sequentially (i.e., one at a time) in any desired order as follows.
Table I of FIG. 2 shows the voltages to be applied to program a selected OTP cell 110 in FIG. 1. The selected OTP cell 110 is the cell that is located in a selected column (SC) and a selected row (SR) of the array. Every other cell in the array is located in either an unselected column (UC) or an unselected row (UR) or both. Table I applies to both the (2×2) array 100 shown in FIG. 1 as well as the larger array (not shown) of which the array 100 is only part.
For example, when the OTP cell 110(m,n) is the selected cell, then the selected column is the mth column (i.e., SC=m), and the selected row is the nth row (i.e., SR=n). In that case, every other column (including the (m+1)th column) is an unselected column (e.g., UC=(m+1)), and every other row (including the (n+1)th row) is an unselected row (e.g., UR=(n+1)).
As shown in Table I, to program a selected OTP cell 110, an appropriate, relatively high, programming voltage Vpp is applied to the programming word line WP of the selected row, a ground voltage (e.g., 0) is applied to the programming word line WP of each unselected row, an appropriate voltage Vinh is applied to the read word line WR of the selected row, a ground voltage is applied to the read word line WR of each unselected row, a ground voltage is applied to the bit line BL of the selected column, and the voltage Vinh is applied to the bit line BL of each unselected column.
With the voltages of Table I applied, for the selected OTP cell 110 in the selected column and the selected row, the access device 112 will be turned on, and a high-voltage difference (i.e., at or near Vpp) will be applied between the gate and source of the anti-fuse device 114, resulting in a permanent breakdown of the gate-oxide layer separating the gate terminal from the source and drain terminals, leaving a permanent conduction path through that gate-oxide layer. In FIG. 1, OTP cell 110(n,m) is a programmed OTP cell having a permanent conduction path 115 through the gate-oxide layer of its anti-fuse device 114.
For each unselected OTP cell 110 in the selected row, but in an unselected column, the access device 112 will be turned on, but the voltage difference between the gate and source of the anti-fuse device 114 will be only (Vpp-Vinh), where Vinh is selected such that the gate-oxide layer of the anti-fuse device 114 will not break down when that gate-to-source voltage difference is applied. For each unselected OTP cell 110 in an unselected row, the access device 112 will be turned off, and the gate-oxide layer of the anti-fuse device 114 will also not break down.
After the array 100 has been programmed, one or more OTP cells 110 will be programmed cells with permanent conduction paths through their anti-fuse gate-oxide layers, while the remaining OTP cells 110 will be unprogrammed cells with their anti-fuse gate-oxide layers intact. The program states of the OTP cells 110 of the programmed array 100 can be determined in any desired order as follows.
Table II of FIG. 2 shows the voltages to be applied in order to read (i.e., determine the program state of) a selected OTP cell 110 in FIG. 1. In particular, an appropriate voltage Vrd is applied to the programming word line WP of the selected row, a ground voltage is applied to the programming word line WP of each unselected row, an appropriate voltage Vdd is applied to the read word line WR of the selected row, a ground voltage is applied to the read word line WR of each unselected row, the voltage Vrd is applied to the bit line BL of each unselected column, and the current in the bit line BL of the selected column is sensed using the sense circuitry for that bit line. In some implementations, Vrd is Vdd. In many implementations, making Vrd the same voltage as Vdd avoids needing separate circuitry to supply a separate Vrd. However, implementations may supply a Vrd different from Vdd.
With the voltages of Table II applied, for the selected OTP cell 110 in the selected column and the selected row, the access device 112 will be turned on. If the selected OTP cell 110 is an unprogrammed cell having an intact anti-fuse gate-oxide layer, then little if any current will flow from the anti-fuse device 114 through the turned-on access device 112 to the bit line BL. If, however, the selected OTP cell 110 is a programmed cell having a permanent conduction path in its anti-fuse gate-oxide layer, then a significant amount of current will flow from the programming word line WP through the permanent conduction path in the anti-fuse device 114 and through the turned-on access device 112 to the bit line BL. Thus, an unprogrammed OTP cell 110 will have a (relatively) low-current state when read, while a programmed OTP cell 110 will have a (relatively) high-current state when read. Depending on the logic applied by the sense circuitry, the low-current state will be interpreted as being either a binary value of 0 or a binary value of 1, while the high-current state will be interpreted as being the other binary value.
For each unselected OTP cell 110 in the selected row, but in an unselected column, the access device 112 will be turned on, but any current in the corresponding (unselected) bit line BL will be ignored. If such an unselected OTP cell 110 is an unprogrammed cell, then little if any current will flow through the intact anti-fuse gate-oxide layer to the unselected bit line BL. If such an unselected OTP cell 110 is a programmed cell, then the voltage Vrd applied to the unselected bit line BL will prevent any significant current from flowing from the program word line WP to that bit line BL.
For each unselected OTP cell 110 in an unselected row, the access device 112 will be turned off, and little if any current will flow to the bit line BL whether the OTP cell 110 is an unprogrammed cell or a programmed cell.
Once an OTP cell 110 is programmed to have a permanent conduction path and a corresponding permanent high-current state, it cannot be subsequently reprogrammed to have a different state.
U.S. Pat. No. 6,700,151, the teachings of which are incorporated herein by reference in their entirety, describes anti-fuse devices that are said to be programmed two times: first by stressing the device's gate oxide until a so-called “soft breakdown” occurs to transition the anti-fuse device from a low-current state to a mid-current state and then subsequently by increasing the breakdown of the gate oxide to transition the cell from the mid-current state to a high-current state.